System and method for full-duplex MAC timing modifications

ABSTRACT

A system, method, and computer-readable storage media for reducing monopolization of a frequency channel during full-duplex communications. The MAC layer of governing communications can be modified to reduce likelihood of monopolization by (1) in networks which are exclusively filled with full-duplex devices, configuring non-communicating devices to ignore data collisions of communicating devices, requiring the communicating devices to wait for an standard backoff time after the data transmission is complete; and/or (2) in mixed half-duplex/full-duplex networks, requiring a half-duplex nodes and/or a full-duplex node to wait an extended duration after the data transmission is complete, while the non-communicating devices do not wait an extended duration.

BACKGROUND

1. Technical Field

The present disclosure relates to full-duplex media access control (MAC)timing modification, and more specifically to ensuring that node pairsinvolved in full-duplex communications do not receive an unfairadvantage of capturing the full-duplex channel repeatedly over nodescommunicating in a half-duplex mode.

2. Introduction

In 802.11 wireless networks, various durations for specific actions andevents are defined. The durations often change depending on protocolversion (for example, version 802.11(a) versus version 802.11(n)),however the relationships of the defined durations do not change.Examples of durations defined within the 802.11 model are SIFS (shortinterframe space), DIFS (distributed coordination function interframespace), and EIFS (extended interframe space). The relationships of theexemplary durations, as defined by the 802.11 model, are that a SIFS hasa shorter duration than a DIFS, which in turn has a shorter durationthan an EIFS. For example, the SIFS can have a duration of 10 μs, theDIFS can have a duration of the SIFS duration+(2×a predetermined slottime), and the EIFS can have a duration of the SIFS duration+the DIFSduration+acknowledgment duration. Alternatively, the SIFS can have aduration determined based on transmission and processing delays builtinto the system.

A MAC (media access control) layer defines how nodes communicate withother nodes using a specific protocol version. MAC layers for the 802.11model and other wireless networks specify that nodes will pause for alonger wait time (EIFS), rather than the standard wait time (DIFS), whenthe nodes receive an erroneous packet. The purpose of the extended waittime upon receiving an erroneous packet is to allow other packetrecipient nodes, who received the data correctly, to be able to send anacknowledgment frame in time.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example system embodiment;

FIG. 2 illustrates an exemplary network having both half-duplex andfull-duplex devices;

FIG. 3 illustrates an example of potential frequency channelmonopolization using MAC frames associated with 802.11(a);

FIG. 4 illustrates an example of MAC frames according to a firstembodiment;

FIG. 5 illustrates an example of MAC frames according to a secondembodiment;

FIG. 6 illustrates a first example method embodiment; and

FIG. 7 illustrates a second example method embodiment.

DETAILED DESCRIPTION

The following disclosure covers two general embodiments that relate tohow nodes in a network communication. A first embodiment relates tonodes communicating in a full-duplex mode. A second embodiment focuseson a scenario where a half-duplex node is communicating in a networkwhere other full-duplex nodes are involved in full-duplex communication.In the second embodiment, the half-duplex node ignores what it wouldnormally view as collisions with respect to how it handles the interfacespacing. Knowledge about the other nodes being in full-duplexcommunication can be explicitly communicated or inferred by thehalf-duplex node.

As noted above, the first embodiment covers full-duplex communicationbetween two nodes. A system, method, computer-readable media, and acomputer-readable device reduce the likelihood of monopolization of afrequency channel by full-duplex devices by modifying the MAC layer. Ina network where all nodes are configured to be full-duplex capable, theMAC can be modified such that upon termination of the communicationbetween the full-duplex devices, the devices which just finishedcommunicating defer (wait) for an EIFS duration prior to engaging in thenext contention round. The other nodes in the network, which were notcommunicating and which viewed the full-duplex data as collisions,similarly pause for an EIFS. Because all of the nodes in the networkpause for an EIFS, the likelihood of channel monopolization by the twocommunicating full-duplex nodes is reduced.

When full-duplex capable nodes are introduced to a network, data can betransmitted by two separate nodes simultaneously in a single frequencychannel. For example, as illustrated in FIG. 2, a network 200 whichcontains half-duplex devices 208 (which are only capable of half-duplexcommunications 210, or are only communicating in a half-duplex mode) hasfull-duplex devices 204 (which are capable of full-duplex communications206) introduced into the network 200. The half-duplex devices 208 andthe full-duplex devices 204 all communicate with an access point 202,which can be a router, base station, or other centralized communicationnode, or with another wireless device (not illustrated). The network 200as illustrated can provide increased communications efficiency,throughput, and/or bandwidth, while allowing for both full-duplex andhalf-duplex nodes. However, while full-duplex communications can bebeneficial to a network, current MAC layer designs specify that whenmultiple packets are received on a single frequency channel frommultiple sources, a collision or error has occurred. Therefore, whilethe full-duplex capable nodes communicating will not detect any errorsand will, following communication, back off for the standard DIFS timeperiod, the remaining nodes in the network will see an error and backofffor an extended EIFS time period. After waiting for the standard DIFStime period, the nodes which had been communicating can begin contendingfor the next round of communications, while the remaining nodes wait forthe EIFS period before beginning contention. Because the DIFS wait timeis smaller than the EIFS wait time, there is a higher likelihood thatone of the full-duplex nodes which had been communicating will grab thechannel again, producing additional interference, and unfairlymonopolizing the frequency channel.

FIG. 3 illustrates the potential for nodes to monopolize the frequencychannel. A full-duplex sender 302 and full-duplex receiver 304 have wona contention round, allowing them access to the frequency channel. Afterwaiting a DIFS period of time 308, the sender 302 sends arequest-to-send signal 310, indicating that the node 302 is ready totransmit data. After a SIFS (short interframe space) 312, the receivingnode sends a clear-to-send 314, indicating both that the sender node 302can send data and also that the receiver node 304 has data it will betransmitting in the same frequency channel, creating a full-duplexcommunication. After another SIFS 316, both nodes 302, 304 initiatecommunication of the data 318, 320. Upon completing the datatransmission, the nodes 302, 304 pause for another SIFS 326, andtransmit acknowledgments 328, 330 if the data 318, 320 was receivedcorrectly. Assuming the data was received correctly, the sender 302 andreceiver 304 both wait for a standard DIFS 332, 334 period of timebefore initiating the next round of communications.

However, the other nodes 306 in the network, which are either notfull-duplex capable or are configured using non-full-duplex MAC layers,see the full-duplex communications as errors. For example, other nodes306 receive, during the RTS-CTS handshake 310, 314, network allocationvectors (NAVs) 322, 324 indicating the estimated packet sizes the sender302 and receiver 304 will be communicating. However, upon thefull-duplex communications beginning with the transmissions of data 318,320, the other nodes 306 receive packets intended for two distinct nodes302, 304, and determine that an error has occurred. Therefore, at timet₃, when the sender 302 and receiver 304, have finished communicationsand begin waiting the standard DIFS 332, 334, which will end at time t₄.The other nodes 306 begin, at time t₃, to wait for the extended EIFS336, which will end at time t₅. The gap 338 between when the DIFS endsat time t₄ and when the EIFS ends at time t₅ can produce unfairness incapturing the channel, because the nodes which wait for the DIFS timeperiod can re-capture the channel, never providing the other nodes 306the opportunity to communicate data. In a network that has bothfull-duplex and half-duplex nodes, the MAC layer is modified such thatthe nodes which were transmitting in full-duplex wait, upon completingtransmission, for an EIFS duration of time, whereas the other nodeswhich were detecting “collisions” either immediately begin contendingfor the next communication round, or alternatively, wait for a DIFSduration before beginning the contention round.

These and other various embodiments are described in detail below. Whilespecific implementations are described, it should be understood thatthis is done for illustration purposes only. Other components andconfigurations may be used without parting from the spirit and scope ofthe disclosure. A brief introductory description of a basic generalpurpose system or computing device in FIG. 1 which can be employed topractice the concepts, methods, and techniques disclosed is illustrated.A more detailed description of modifications to the MAC layers toprevent unfairness, as well as various embodiments and configurations,will then follow. These variations shall be described herein as thevarious embodiments are set forth. The disclosure now turns to FIG. 1.

With reference to FIG. 1, an exemplary system and/or computing device100 includes a processing unit (CPU or processor) 120 and a system bus110 that couples various system components including the system memory130 such as read only memory (ROM) 140 and random access memory (RAM)150 to the processor 120. The system 100 can include a cache 122 of highspeed memory connected directly with, in close proximity to, orintegrated as part of the processor 120. The system 100 copies data fromthe memory 130 and/or the storage device 160 to the cache 122 for quickaccess by the processor 120. In this way, the cache provides aperformance boost that avoids processor 120 delays while waiting fordata. These and other modules can control or be configured to controlthe processor 120 to perform various actions. Other system memory 130may be available for use as well. The memory 130 can include multipledifferent types of memory with different performance characteristics. Itcan be appreciated that the disclosure may operate on a computing device100 with more than one processor 120 or on a group or cluster ofcomputing devices networked together to provide greater processingcapability. The processor 120 can include any general purpose processorand a hardware module or software module, such as module 1 162, module 2164, and module 3 166 stored in storage device 160, configured tocontrol the processor 120 as well as a special-purpose processor wheresoftware instructions are incorporated into the processor. The processor120 may be a self-contained computing system, containing multiple coresor processors, a bus, memory controller, cache, etc. A multi-coreprocessor may be symmetric or asymmetric.

The system bus 110 may be any of several types of bus structuresincluding a memory bus or memory controller, a peripheral bus, and alocal bus using any of a variety of bus architectures. A basicinput/output (BIOS) stored in ROM 140 or the like, may provide the basicroutine that helps to transfer information between elements within thecomputing device 100, such as during start-up. The computing device 100further includes storage devices 160 such as a hard disk drive, amagnetic disk drive, an optical disk drive, tape drive or the like. Thestorage device 160 can include software modules 162, 164, 166 forcontrolling the processor 120. The system 100 can include other hardwareor software modules. The storage device 160 is connected to the systembus 110 by a drive interface. The drives and the associatedcomputer-readable storage media provide nonvolatile storage ofcomputer-readable instructions, data structures, program modules andother data for the computing device 100. In one aspect, a hardwaremodule that performs a particular function includes the softwarecomponent stored in a tangible computer-readable storage medium, or in acomputer-readable storage device, in connection with the necessaryhardware components, such as the processor 120, bus 110, display 170,and so forth, to carry out a particular function. In another aspect, thesystem can use a processor and computer-readable storage medium to storeinstructions which, when executed by the processor, cause the processorto perform a method or other specific actions. The basic components andappropriate variations can be modified depending on the type of device,such as whether the device 100 is a small, handheld computing device, adesktop computer, or a computer server.

Although the exemplary embodiment(s) described herein employs the harddisk 160, other types of computer-readable media which can store datathat are accessible by a computer, such as magnetic cassettes, flashmemory cards, digital versatile disks, cartridges, random accessmemories (RAMs) 150, read only memory (ROM) 140, a cable or wirelesssignal containing a bit stream and the like, may also be used in theexemplary operating environment. Tangible computer-readable storagemedia, or computer-readable storage devices, expressly exclude mediasuch as energy, carrier signals, electromagnetic waves, and signals perse.

To enable user interaction with the computing device 100, an inputdevice 190 represents any number of input mechanisms, such as amicrophone for speech, a touch-sensitive screen for gesture or graphicalinput, keyboard, mouse, motion input, speech and so forth. An outputdevice 170 can also be one or more of a number of output mechanismsknown to those of skill in the art. In some instances, multimodalsystems enable a user to provide multiple types of input to communicatewith the computing device 100. The communications interface 180generally governs and manages the user input and system output. There isno restriction on operating on any particular hardware arrangement andtherefore the basic hardware depicted may easily be substituted forimproved hardware or firmware arrangements as they are developed.

For clarity of explanation, the illustrative system embodiment ispresented as including individual functional blocks including functionalblocks labeled as a “processor” or processor 120. The functions theseblocks represent may be provided through the use of either shared ordedicated hardware, including, but not limited to, hardware capable ofexecuting software and hardware, such as a processor 120, that ispurpose-built to operate as an equivalent to software executing on ageneral purpose processor. For example the functions of one or moreprocessors presented in FIG. 1 may be provided by a single sharedprocessor or multiple processors. (Use of the term “processor” shouldnot be construed to refer exclusively to hardware capable of executingsoftware.) Illustrative embodiments may include microprocessor and/ordigital signal processor (DSP) hardware, read-only memory (ROM) 140 forstoring software performing the operations described below, and randomaccess memory (RAM) 150 for storing results. Very large scaleintegration (VLSI) hardware embodiments, as well as custom VLSIcircuitry in combination with a general purpose DSP circuit, may also beprovided.

The logical operations of the various embodiments are implemented as:(1) a sequence of computer implemented steps, operations, or proceduresrunning on a programmable circuit within a general use computer, (2) asequence of computer implemented steps, operations, or proceduresrunning on a specific-use programmable circuit; and/or (3)interconnected machine modules or program engines within theprogrammable circuits. The system 100 shown in FIG. 1 can practice allor part of the recited methods, can be a part of the recited systems,and/or can operate according to instructions in the recited tangiblecomputer-readable storage media. Such logical operations can beimplemented as modules configured to control the processor 120 toperform particular functions according to the programming of the module.For example, FIG. 1 illustrates three modules Mod1 162, Mod2 164 andMod3 166 which are modules configured to control the processor 120.These modules may be stored on the storage device 160 and loaded intoRAM 150 or memory 130 at runtime or may be stored in othercomputer-readable memory locations.

Having disclosed some components of a computing system, and havingdiscussed FIGS. 2 and 3 above, the disclosure provides exemplaryembodiments. While these embodiments are discussed separately, elementsand pieces of each embodiment can be combined without violation of theprinciples disclosed herein. FIG. 4 illustrates an example of MAC framesaccording to a first embodiment. A full-duplex sender 402 has won acontention round with a full-duplex sender 404. After waiting for a DIFSduration 408, the sender 402 and receiver engage in a RTS-CTS handshake410 prior to initiate communication of data. Other full-duplex nodes 406recognize the signals exchanged in the RTS-CTS handshake, and recognizethe NAV durations 422, 424 indicated within the RTS and CTS signals.

As the sender 402 and receiver 404 exchange data 418, 420 infull-duplex, the other nodes 406 receive two sets of data packets, whichis recorded as a collision per previous MAC layer designs. Uponfinishing the data transmissions 418, 420, the sender 402 and receiver404 pause for a SIFS duration 426, and transmit acknowledgements of thedata received 428, 430. Following the transmission of acknowledgments,at time t₃, the sender 402 and receiver 404 pause an EIFS duration 432,434 prior to entering a new contention round. The other full-duplexnodes 406, which have been recording collisions during the process,recognize the end of the data exchange, at time t₃, and also wait for anEIFS 436. Recognition of the end of the data exchange can occur based onreceiving the transmitted acknowledgments 428, 430, or based on thetermination of the NAV durations 422, 424 previously received.

In other configurations the other nodes 406 can be half-duplex nodes, oralternatively, a mixture of full-duplex and half-duplex nodes. Inaddition, the MAC can be modified such that the other nodes 406 wait fora shorter duration than an EIFS, such as a DIFS, an SIFS, or for asshort a duration as logistically possible, prior to initiating the nextcontention round. Because the sender 402 and receiver 404 nodes areconfigured to wait for an EIFS, these shorter durations can provide anadvantage to the other nodes 406 in “winning” the contention round.

The second embodiment disclosed herein covers a configuration where ahalf-duplex node is communicating in a network where at least one othernode is communicating in a full duplex mode. FIG. 5 illustrates anexample of MAC frames according to the second embodiment. A full-duplexsender 502 has won a contention round for access to a full-duplexreceiver 504. After waiting for a DIFS duration 508, the sender 502 andreceiver 504 engage in a RTS-CTS handshake 510 prior to initiatecommunication of data. Other half-duplex nodes 506 recognize the signalsexchanged in the RTS-CTS handshake, and recognize the NAV durations 522,524 indicated within the RTS and CTS signals. As the sender 502 andreceiver 504 exchange data 518, 520 in full-duplex, the otherhalf-duplex nodes 506 receive two sets of data packets, which areconsidered collisions, just as previous MAC layer designs havespecified. Alternatively, the other half-duplex nodes 506 (and/oradditional full-duplex nodes in the network) can ignore the collisions,rather than recording the collisions, until the end of the NAV durationsreceived. The information about the full-duplex transfer can be inferredby a half-duplex node in some fashion. One example of how thehalf-duplex node would infer data about a full-duplex transfer viaanother node is through information in the CTS packet or through otherdata. Further, other full-duplex capable nodes and/or full-duplex nodesin a full-duplex communication mode may also have explicit informationabout or inferred information about a set of nodes in full-duplexcommunication such that the other full-duplex capable node and/orfull-duplex nodes in a full-duplex communication mode also ignorecollisions in the NAV duration from the set of nodes in full-duplexcommunication.

Upon finishing the data transmissions 518, 520, the sender 502 andreceiver 504 pause for a SIFS duration 526, and transmitacknowledgements of the data received 528, 530. Following thetransmission of acknowledgments 528, 530, at time t₃, the sender 502 andreceiver 504 pause an EIFS duration 532, 534 prior to entering a newcontention round. The other half-duplex nodes 506, which have beenregistering collisions during the full-duplex exchange process orignoring the collisions, recognize the end of the data exchange. Therecognition can occur based on receiving the acknowledgments 528, 530transmitted, or based on the termination of the NAV durations 522, 524previously received. At time t₃, upon recognizing that the data exchangehas ended, the other half-duplex nodes 506 do not wait for an EIFS, butinstead wait for a DIFS duration 536. After the DIFS duration 536, theother half-duplex nodes 506 can immediately initiate a new contentionround, decreasing the likelihood of the nodes which sent and receiveddata 502, 504 in the previous round re-winning the contention round. Incertain configurations, at time t₃ the other half-duplex nodes 506 donot wait for a DIFS or an EIFS, instead immediately initiating the newcontention round.

Having disclosed some basic system components and concepts, thedisclosure now turns to the first exemplary method embodiment shown inFIG. 6. For the sake of clarity, the method is described in terms of anexemplary system 100 as shown in FIG. 1 configured to practice themethod. The steps outlined herein are exemplary and can be implementedin any combination thereof, including combinations that exclude, add, ormodify certain steps.

The system 100 first determines that a first node and a second node arein full-duplex communication, wherein the first node uses a distributedchannel access protocol for contending with other nodes to communicatewith the second node (602). For example, the first node uses thedistributed channel access protocol to win a contention round. Winningthe contention round can be based on strength of signal, priority ofdata, time since last communication, or other factors having a relativeweight higher than factors belonging to other nodes. The system 100, forexample, can be the first node or the second node. Examples of the firstnode and second node can be wireless devices, such as smartphones,tablet computers, laptops, and wireless routers. Therefore, if thesystem 100, acting as the first node, is a smartphone and the secondnode is a wireless router, per step 602 the system 100 wins thecontention round using a distributed channel access protocol and beginsfull-duplex communications with the router.

After receiving an acknowledgment of receipt of a successfultransmission from the second node, the system 100 defers, or waits, foran extended interframe space (604). The extended interframe space islonger than the standard distributed coordination function interframespace, or DCF interframe space, between rounds of communication. Forexample, the DCF interframe space could have a duration of 50 μs,whereas the extended interframe space is longer than 50 μs. In certainconfigurations, the system 100 can receive instructions directing it towait for the extended interframe space based on the other nodes, whereasin other configurations the MAC layer associated with the system 100 canbe permanently modified such that communications the system 100 alwaysdefers, after receiving acknowledgment of receipt of data, for anextended interframe space. As an example of a signal that could be usedto indicate that an extended interframe space duration should follow, aCTS sender can indicate that it intends to send full-duplex data byre-purposing an unused bit (e.g., the More Data bit in the CTS FrameControl field). The unused bit can indicate that the modified version ofthe MAC should be used. Another option is for a full-duplex node to usetwo MAC addresses, one for half-duplex use, and the other forfull-duplex use. Having two MAC addresses would allow the RTS sender toadapt its rate based on which MAC address, the full-duplex orhalf-duplex, is being used, and the new duration using that adapted ratecould be set as a NAV duration by the CTS sender.

The other nodes associated with the system 100, which did not win thecontention round, can be configured to immediate begin contending forthe next round of communications, or can be configured to wait for aDIFS, an EIFS, or another time duration. The interframe spacingdurations, such as DIFS, EIFS, or SIFS, used by the system 100 can beset by a standard or model, such as the 802.11 standard.

FIG. 7 illustrates a second exemplary method embodiment. As with FIG. 6,for the sake of clarity, the method is described in terms of anexemplary system 100 as shown in FIG. 1 configured to practice themethod. The steps outlined herein are exemplary and can be implementedin any combination thereof, including combinations that exclude, add, ormodify certain steps.

The system 100, at a first node, determines that a second node and athird node are in full duplex communication, wherein the first node andthe second node use a distributed channel access protocol for contendingfor access to communicate with the third node (702). The nodes can belaptops, smartphones, tablets, base stations, or other wireless devices.Contending for access can take place via a contention round, in whichall of the nodes contend for the ability to communicate data with thethird node.

After receiving, at the first node, a communication associated with thefull-duplex communication between the second node and the third node,the full-duplex communication not intended for the first node, thesystem 100 defers for a distributed coordination function interframespace period of time (704). In order for the system 100 to defer for adistributed coordination function interframe space duration, the MAClayer of the system 100 can be modified. An exemplary modification canrequire the distributed coordination function interframe space durationto always be initiated following the reception of non-intended data, or,in other configurations, the signal can indicate that the distributedcoordination function interframe space duration should be used.

As an example of a signal that could be used to indicate that adistributed coordination function interframe space duration shouldfollow a communication, a CTS sender can indicate that it intends tosend full-duplex data by re-purposing an unused bit (e.g., the More Databit in the CTS Frame Control field). The unused bit can indicate thatthe modified version of the MAC should be used. Another option is for afull-duplex node to use two MAC addresses, one for half-duplex use, andthe other for full-duplex use. Having two MAC addresses would allow theRTS sender to adapt its rate based on which MAC address, the full-duplexor half-duplex, is being used, and the new duration using that adaptedrate could be set as a NAV duration by the CTS sender.

The system 100 can, following the distributed coordination functioninterframe space duration, enter a new contention round. While the firstnode defers for a distributed coordination function interframe spaceperiod of time, the second and third nodes can be configured to wait foran extended interframe space duration following a communication. Thesystem 100 can initiate the subsequent contention round prior to thesecond node and the third node completing the extended interframe space“pause,” and thereby prevents unfair monopolization of the frequencychannel (used in full-duplex communications) by the second and thirdnodes. The interframe spacing durations, such as DIFS, EIFS, or SIFS,used by the system 100 can be set by a standard or model, such as the802.11 standard.

Embodiments within the scope of the present disclosure may also includetangible and/or non-transitory computer-readable storage media forcarrying or having computer-executable instructions or data structuresstored thereon. Such tangible computer-readable storage media can be anyavailable media that can be accessed by a general purpose or specialpurpose computer, including the functional design of any special purposeprocessor as described above. By way of example, and not limitation,such tangible computer-readable media can include RAM, ROM, EEPROM,CD-ROM or other optical disk storage, magnetic disk storage or othermagnetic storage devices, or any other medium which can be used to carryor store desired program code means in the form of computer-executableinstructions, data structures, or processor chip design. Wheninformation is transferred or provided over a network or anothercommunications connection (either hardwired, wireless, or combinationthereof) to a computer, the computer properly views the connection as acomputer-readable medium. Thus, any such connection is properly termed acomputer-readable medium. Combinations of the above should also beincluded within the scope of the computer-readable media.

Computer-executable instructions include, for example, instructions anddata which cause a general purpose computer, special purpose computer,or special purpose processing device to perform a certain function orgroup of functions. Computer-executable instructions also includeprogram modules that are executed by computers in stand-alone or networkenvironments. Generally, program modules include routines, programs,components, data structures, objects, and the functions inherent in thedesign of special-purpose processors, etc. that perform particular tasksor implement particular abstract data types. Computer-executableinstructions, associated data structures, and program modules representexamples of the program code means for executing steps of the methodsdisclosed herein. The particular sequence of such executableinstructions or associated data structures represents examples ofcorresponding acts for implementing the functions described in suchsteps.

Other embodiments of the disclosure may be practiced in networkcomputing environments with many types of computer systemconfigurations, including personal computers, hand-held devices,multi-processor systems, microprocessor-based or programmable consumerelectronics, network PCs, minicomputers, mainframe computers, and thelike. Embodiments may also be practiced in distributed computingenvironments where tasks are performed by local and remote processingdevices that are linked (either by hardwired links, wireless links, orby a combination thereof) through a communications network. In adistributed computing environment, program modules may be located inboth local and remote memory storage devices.

The various embodiments described above are provided by way ofillustration only and should not be construed to limit the scope of thedisclosure. For example, the principles herein apply equally to wirelesscommunications and cellular communications where practical. Variousmodifications and changes may be made to the principles described hereinwithout following the example embodiments and applications illustratedand described herein, and without departing from the spirit and scope ofthe disclosure.

We claim:
 1. A method comprising: determining, at a first node, that thefirst node and a second node are in full-duplex communication, whereinthe first node uses a distributed channel access protocol for contendingwith other nodes to communicate with the second node; receiving an inputindicating that the use of an extended interframe space should be usedrather than a distributed coordination function interframe space,wherein the input is received as part of a clear-to-send signal; andafter receiving an acknowledgment of receipt of a successfultransmission from the second node, deferring contention in thedistributed channel access protocol at the first node for the extendedinterframe space, wherein the extended interframe space delays the firstnode from entering, at a start time, a subsequent contention round. 2.The method of claim 1, wherein, after transmitting the acknowledgment ofreceipt of the successful transmission, the second node deferscontention in the distributed channel access protocol for the extendedinterframe space.
 3. The method of claim 2, wherein the wireless deviceis one of a smartphone, a laptop, a router, and a computer.
 4. Themethod of claim 1, wherein a duration of the extended interframe spaceis defined by an 802.11 standard.
 5. The method of claim 1, wherein thefirst node does not transmit data in a subsequent full-duplexcommunication round.
 6. A system comprising: a processor; and acomputer-readable storage medium having instructions stored which, whenexecuted by the processor, cause the processor to perform operationscomprising: determining, at a first node, that the first node and asecond node are in full-duplex communication, wherein the first nodeuses a distributed channel access protocol for contending with othernodes to communicate with the second node; receiving an input indicatingthat the use of an extended interframe space should be used rather thana distributed coordination function interframe space, wherein the inputis received as part of a clear-to-send signal; and after receiving anacknowledgment of receipt of a successful transmission from the secondnode, deferring contention in the distributed channel access protocol atthe first node for the extended interframe space, wherein the extendedinterframe space delays the first node from entering, at a start time, asubsequent contention round.
 7. The system of claim 6, wherein, aftersending the acknowledgement of the successful transmission, the secondnode defers from contention in the distributed channel access protocolfor the extended interframe space.
 8. The system of claim 7, wherein thewireless device is one of a smartphone, a laptop, a router, and acomputer.
 9. The system of claim 7, wherein a duration of the extendedinterframe space is defined by an 802.11 standard.
 10. The system ofclaim 8, wherein the first node does not transmit data in a subsequentfull-duplex communication round.
 11. A computer-readable storage devicehaving instructions stored which, when executed by a computing device,cause the computing device to perform operations comprising:determining, at a first node, that the first node and a second node arein full-duplex communication, wherein the first node uses a distributedchannel access protocol for contending with other nodes to communicatewith the second node; receiving an input indicating that the use of anextended interframe space should be used rather than a distributedcoordination function interframe space, wherein the input is received aspart of a clear-to-send signal; and after receiving an acknowledgment ofreceipt of a successful transmission from the second node, deferringcontention in the distributed channel access protocol at the first nodefor the extended interframe space, wherein the extended interframe spacedelays the first node from entering, at a start time, a subsequentcontention round.
 12. The computer-readable storage device of claim 11,wherein the second node, after transmitting the acknowledgment ofreceipt of the successful transmission, defers from contention in thedistributed channel access protocol for the extended interframe space.13. The computer-readable storage device of claim 12, wherein thewireless device is one of a smartphone, a laptop, a router, and acomputer.
 14. The computer-readable storage device of claim 12, whereina duration of the extended interframe space is defined by an 802.11standard.